The present invention relates generally to communications interfaces. More particularly the present invention relates to communications interfaces for communication between communication buses operating at different clock speeds.
In many modern data processing systems, a processor communicates with other local devices utilizing a high speed communications bus. Thus, for example, processors may communicate with internal cache or other such high speed functions over the high speed communications bus. Problems may arise, however, when a peripheral cannot or need not operate at the clock rate of the high speed communications bus. In such a case it has been conventional to provide separate communications buses which operate at lower speeds to accommodate such lower speed peripherals. Such peripherals may be integrated with the processor or they may be external to the processor. In any event, the difference in clock speeds of the high speed bus utilized by the processor and the lower speed peripheral bus may result in increased hardware and more complex systems to accommodate the various bus speeds.
In more complex systems, peripherals requiring differing bus speeds may be utilized in the same system. Thus, in such systems the capability to communicate from differing slower speed buses to a higher speed bus is generally required. This addition of multiple slower speed buses may further complicate the system as the system must take into account the characteristics of each slower speed bus.
For example, in providing Direct Memory Access (DMA) functions between buses of differing speeds it has been conventional to provide a DMA controller for each bus which interfaces between the differing bus speeds using a third bus common to both controllers. One such system is described in U.S. Pat. No. 5,664,142 to Boldt et al. This system, however, would utilize a DMA controller for each bus speed. Furthermore, the bus speed is typically required to be known in advance which may limit the flexibility of the Boldt et al. system.
Additional interfaces between different speed buses are found in U.S. Pat. Nos. 5,125,084, 5,142,672 5,428,751 and 5,561,821. However, these references all utilize DMA devices which operate at fixed speeds, thus increasing the complexity of utilizing these systems where peripherals on multiple slower speed buses communicate with a higher speed bus.
In light of the above discussion, a need exists for improvements in communications between buses operating at differing speeds.
In view of the above it is one object of the present invention to provide a communication interface which allows for communications with buses of differing speeds.
A further object of the present invention is to provide for communications with differing speed buses utilizing a common controller for the differing speed buses.
Still another object of the present invention is to provide communications at the clock speed of each bus of differing clock speed buses.
Another object of the present invention is to provide a communication system which may be adjusted from system to system without requiring modifications to the controller.
In view of these and other objects of the present invention, the present invention provides a communication system for use in data processing systems for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received from a device associated with a clock domain of the second bus. The speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur at the second clock speed.
The dynamic adjustment may be accomplished by gating a clock operating at the first clock speed which clocks a state machine of a peripheral controller with the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur at the second clock speed. Thus, data may be provided to and received from the first bus at the first clock speed and data may be provided to and received from the second bus at the second clock speed. Furthermore, the gating may be accomplished by a logical ANDing of the sample signal with clock pulses at the first clock speed so as to create a clock of the second clock speed.
By dynamically adjusting the speed of the controller, a communication interface which allows for communications with buses of differing speeds is provided. Furthermore, a common controller for the differing speed buses may be utilized because the speed of the controller is adjusted to the speed of the second bus. The present invention also provides communications on each bus of differing clock speed buses at the clock speed of the bus. Also, because the controller is dynamically adjusted to the speed of the bus, the controller may accommodate differing bus speeds without requiring modifications to the controller.
In particular embodiments of the present invention, the sample signal is generated so as to be active during a cycle of the clock at the first clock speed immediately prior to a transition of the clock at the second clock speed.
In further embodiments, the first bus is an internal bus and the second bus is an external bus. Also, the peripheral controller may be a DMA controller.
In still another embodiment of the present invention, the peripheral controller further controls communications between the first bus and a second peripheral device associated with a third bus which operates at a third clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. In such a case, a second sample signal associated with the third clock speed is received from the second peripheral and the speed of operation of the state machine of the peripheral controller is dynamically adjusted in response to the second sample signal such that the state machine of the peripheral controller operates at the third clock speed and causes operations on the third data bus to occur at the third clock speed. Furthermore, the adjustment of the speed of operation of the state machine may be achieved by gating the clock operating at the first clock speed which clocks the state machine of the peripheral controller with the second sample signal so as to provide clock pulses to the state machine at the third clock speed such that the state machine of the peripheral controller causes operations on the third data bus to occur at the third clock speed. The second clock speed and the third clock speed may be different clock speeds.
In a further embodiment of the present invention, a communication system for allowing DMA communication between multiple buses is provided which includes a first bus utilizing a first clock operating at a first clock speed and a second bus utilizing a second clock operating at a second clock speed wherein the second clock speed is different from the first clock speed and is a 1/N integer multiple of the first clock speed. A first bridge slave transmits and receives data to and from the first bus and transmits and receives data to and from the second bus. The bridge slave provides a first sample signal corresponding to the second clock speed. A DMA master operably associated with the first bridge slave and which generates control signals for controlling communications to and from the first and second buses, includes a DMA state machine corresponding to a transfer state on the second bus. The DMA state machine is clocked by the first clock gated with the first sample signal from the first bridge slave so as to clock the DMA state machine at the second clock speed.
In a further embodiment, the first bridge slave includes means for generating the first sample signal so as to be active during a cycle of the first clock immediately prior to a transition of the second clock. The DMA master may also include an AND gate for ANDing the first sample signal with the first clock so as to create a clock operating at the second clock frequency.
In particular embodiments, the first bus is an internal bus and the second bus is an external bus. In still another embodiment, the first bridge slave transmits and receives data to and from the first bus at the first clock speed and transmits and receives data from the second bus at the second clock speed.
A further embodiment of the present invention includes a third bus utilizing a third clock operating at a third clock speed wherein the third clock speed is a 1/N integer multiple of the first clock speed. A second bridge slave transmits and receives data to and from the first bus and transmits and receives data to and from the third bus. The bridge slave further provides a second sample signal corresponding to the third clock speed. The DMA master is further operably associated with the second bridge slave and generates control signals for controlling communications to and from the first and third buses. The DMA state machine is clocked by the first clock gated with the first sample signal from the first bridge slave so as to clock the DMA state machine at the second clock speed when communicating between the first and second buses. The DMA state machine is clocked by the first clock gated with the second sample signal from the second bridge slave so as to clock the DMA state machine at the third clock speed when communicating between the first and third buses. In a particular embodiment, the second and third clock speed are different clock speeds.
As will be appreciated by those of skill in the art, the present invention may further take the form of slave, and/or master functions capable of carrying out the above described operations. Furthermore, the present invention may be embodied as methods or systems for controlling communications or as a peripheral controller.